TSMC unveils 1.6nm process technology with backside power delivery

Backside Power Delivery (BSPDN)

• Power and signal wiring are separated onto opposite sides of the silicon wafer.
• Transistors sit “in the middle,” with thick, low‑resistance power wires on the back and fine signal interconnect on the front.
• Benefits discussed: less interference (capacitance) between power and signal, cleaner power, shorter signal routes, more routing area, and lower power use at a given performance.
• Drawbacks / challenges: harder thermal management and very difficult fabrication (precise through‑wafer vias, contamination control, extra process steps).
• Several commenters note it’s conceptually obvious but only now economically and technically feasible (driven by extreme scaling, higher power density, and maturing through‑wafer / 3D‑IC techniques).

Impact on Performance, Power, and AI/HPC

• Highlighted spec: ~15–20% lower power at same performance/complexity vs N2, considered the most impressive aspect.
• BSPDN is described as especially useful for AI and high‑performance computing chips, which have dense, highly utilized logic and complex wiring plus very heavy power demands.
• Contrast made with mobile/low‑power processes historically optimized more for efficiency than raw speed.

Process Node Naming and Metrics

• Long subthread argues current “nm” labels are largely marketing and no longer track any specific physical dimension (gate length, half‑pitch, etc.).
• Some see the labels as nearly meaningless, others as a rough shorthand for “newer, denser, better” similar to car horsepower.
• Suggestions for better metrics: transistor density (MTr/mm²), power‑normalized density, or mm² per transistor.
• Example numbers cited: TSMC around 197 MTr/mm² now, ~230 MTr/mm² projected for 1.6 “nm”; Intel and Samsung currently lower.

TSMC vs Intel (and Samsung) Roadmaps

• Thread frames this node as a competitive response to Intel’s 18A (also ~2026), with both sides planning backside power.
• Disagreement over who is “ahead”: some note Intel first pushed BSPDN commercially; others emphasize TSMC’s stronger recent execution and higher current densities.
• Skepticism about Intel’s timelines is common, given past slips; others argue their adoption of High‑NA EUV and potential DSA could let them leapfrog if it works.

Manufacturing Technology and Constraints

• EUV tools from ASML (including new High‑NA systems) are central; history notes US lab origins of EUV and export controls limiting sales to China.
• Commenters stress that lithography advances, patterning tricks (double patterning, DSA), and yield/cost per wafer are now as important as nominal “node size.”