Optical PCIe 7.0 connection hits 128 GT/s

Original Article ↗ Hacker News Discussion ↗

An announcement of an optical PCIe 7.0 interface running at 128 GT/s prompts debate over what that number really means in terms of usable bandwidth, how “gigatransfers per second” differ from gigabits, and how protocol encoding and error correction affect throughput. Commenters explore why high-speed links are still mostly electrical despite growing signal integrity problems, weighing the cost, size, power, fabrication, and latency tradeoffs between copper and silicon photonics. Many see datacenter use cases—GPU/AI interconnects, fast NVMe storage, and high-speed networking—as the main drivers for these advances, while noting that ever-rising bandwidth does not automatically translate into lower end-user latency.

Meaning of GT/s and Effective Bandwidth

  • GT/s = gigatransfers per second at the physical layer, essentially “raw bits on the wire,” not directly usable data.
  • Older PCIe generations used line encoding with overhead:
    • PCIe 1.0–2.0: 8b/10b (≈20% overhead).
    • PCIe 3.0–5.0: 128b/130b (≈1.5% overhead).
  • PCIe 6.0–7.0 use PAM4 signaling plus FEC with ≈single‑digit overhead, but the details are more complex.
  • 128 GT/s per lane ≈ 128 Gbit/s raw ≈ 16 GB/s usable per lane, not TB/s.
  • Some posters argue GT/s is a poorly defined unit and mixes up “transfers,” “symbols,” and data rate; others note PCI-SIG explicitly uses GT/s to describe link rate and distinguishes it from Gbit/s due to encoding/FEC.

Optical vs Copper PCIe Interconnects

  • Copper is nearing practical limits at these speeds: severe signal integrity issues, short reach on PCBs, and growing need for power‑hungry retimers and expensive low‑loss board materials.
  • Optical interconnects avoid many SI problems and support long reach with low attenuation and EMI immunity; energy per bit can be favorable at high rates and distances.
  • Current downsides of optics:
    • Transceivers are larger, more power‑hungry, and much more expensive than electrical SERDES.
    • Electro‑optic conversion adds complexity, noise, and power overhead.
    • Photonic waveguides and components are physically larger than electronic ones; co‑integration with high‑performance CMOS is hard.
  • Optical PCIe is most attractive for datacenter/large GPU chassis with long runs; for short on‑board links, copper remains simpler and cheaper.

Performance Drivers and System Design

  • Main drivers for faster PCIe: GPU/AI interconnects, very high‑speed networking (400G→800G→1.6T Ethernet), and dense NVMe storage.
  • Higher PCIe generations let devices use fewer lanes (e.g., a future SSD on x1 instead of x4), freeing lanes for more devices, especially in servers.
  • Bridging between generations (e.g., mapping PCIe 6.0 lanes to 4.0 slots) generally requires extra chips, adding cost and complexity.

Latency vs Bandwidth Debates

  • Several comments stress that PCIe GT/s is about throughput, not latency; a link can have huge bandwidth but still non‑trivial end‑to‑end latency.
  • Others note real system latency also comes from protocol overhead, buffering, error correction, and software (e.g., OS compositors), which often dominates user‑visible responsiveness.

Skepticism About the Announcement

  • Some readers find the article light on technical details (modulation schemes, fiber count, multiplexing) and heavy on marketing adjectives, making the “groundbreaking” nature of the demo unclear.