Ask HN: Weirdest Computer Architecture?

Hacker News Discussion ↗

Scope of “weird architecture”

  • Commenters note that “computer architecture” spans multiple axes: computational models (Turing, analog, neural, cellular automata), ISAs (ARM, x86, RISC‑V), styles (CISC, RISC, VLIW, TTA), addressing schemes (stack vs multi‑address), microarchitecture (pipelining, OoO), and system organization (shared vs distributed memory).
  • What counts as “weirdest” depends on which axis you look at.

Unconventional physical substrates

  • Non‑electronic or hybrid computing: water computers and Soviet water integrators, mechanical fire-control computers, magnetic logic (suggested for extreme environments like Venus), vacuum tubes as clock/power for magnetic logic, pneumatic logic, tinker‑toy computers, crab‑powered logic, and soap‑bubble / annealing‑style optimization.
  • Analog and neuromorphic: general‑purpose analog computers, The Analog Thing, IBM TrueNorth, Mythic’s analog processors, reservoir computing.
  • Biological / speculative: mushroom computing, computing near black holes, DNA and brain‑like systems.

Odd digital ISAs and machines

  • Historic mainframes and minis: VAX (complex but influential), IBM z/Architecture and earlier 360/370 variants, ENIAC (decimal, programmed with cables), IBM 1401 (variable‑length, BCD, card-as-program), Burroughs Large Systems stack machines, ATLAS‑1 with no branch instruction, CDC 6000 barrel processor.
  • Exotic commercial / research chips: Transmeta, Cell, Transputer, Mill CPU, iAPX 432, GreenArrays Forth chips, Parallax Propeller, MC14500B 1‑bit CPU, Apple’s “Scorpius”, Anton MD ASICs. Reactions range from admiration to “brilliant but impractical / too early / too slow.”
  • Lisp machines, Connection Machine, Setun ternary computer, magnetic‑logic and early battlefield machines are cited as especially “out there.”

Parallelism, grids, and reconfigurability

  • BitGrid, GreenArrays, Transputers, PipeRench, Solana’s eBPF “global computer,” and custom grids (e.g., 144‑cell Forth‑style arrays) emphasize massive parallelism and message‑passing.
  • Barrel processors (CDC, Propeller) and networked tiles / cores (including OSs like Barrelfish) show alternative scheduling and multicore models.

Addressing, word size, and data quirks

  • Deep discussion of 24‑/26‑/31‑/32‑bit addressing (IBM 370/XA, 286 protected mode, 68k, ARM1/2), their OS tooling, and hacks (e.g., “MVS/380” using a hybrid S/380 model to build GCC).
  • Weird widths and layouts: 9‑bit bytes and 27‑bit “middle‑endian” words, 11‑bit floats and 7‑bit ints in avionics, 18‑bit Forth machines, 51‑bit tagged words.

Resilient, asynchronous, and non-deterministic models

  • Asynchronous and clockless efforts: AMULET (async ARM), Ivan Sutherland’s clockless computing, and designs where the clock doubles as power.
  • Movable Feast Machine / T2 tiles intentionally embrace unreliable, non‑deterministic local operations, pushing error recovery into software; some find this mind‑bending but potentially important as computation becomes ubiquitous.

Esoteric instruction sets and Turing-completeness

  • x86 MOV‑only computation and the movfuscator, PowerPoint and other “accidentally Turing‑complete” systems.
  • No‑instruction‑set computing (NISC) and transport‑triggered architectures are highlighted as underexplored.
  • zk‑STARK VMs (e.g., TritonVM, Risc0) are cited as esoteric virtual architectures tuned to make program execution provable via cryptographic arithmetization.