RISC-V is currently slow compared to modern CPUs

Original Article ↗ Hacker News Discussion ↗

ISA vs. implementation

  • Many argue the title “RISC‑V is slow” misattributes current performance problems to the ISA rather than immature implementations.
  • Today’s commercial RISC‑V chips are mostly simple, in‑order designs with weaker branch prediction and cache hierarchies, so they naturally lag high‑end x86/Arm cores.
  • Others note that ISA design still matters for how easily high‑performance out‑of‑order (OoO) cores can be built, but RISC‑V was explicitly designed with modern superscalar implementations in mind (no flags, no branch delay slots, etc.).

Benchmarks and comparisons

  • Geekbench results for available RISC‑V boards show single‑thread scores far below Apple M‑series and top x86/Arm; a “25× slower” gap is cited.
  • Several commenters stress this is an unfair comparison: RISC‑V cores have had far less money, time, and leading‑edge nodes invested.
  • Some point to specific cores (e.g., academic or Chinese projects) that already match older x86 generations per‑cycle in simulation or silicon, suggesting the gap is shrinking.
  • Vector/SIMD support and software paths for RISC‑V (RVV) are still young; where hand‑tuned RVV vs Neon is compared, performance can be competitive.

Ecosystem, investment, and trajectory

  • There is debate over whether RISC‑V will ever attract enough capital to reach top‑end Arm/x86 performance.
  • Some expect strong momentum from the US, China, Europe, and industrial users (e.g., long‑lived equipment, supercomputing) who value a royalty‑free ISA.
  • Others argue that for many uses (routers, embedded controllers, small SBCs) “good enough + cheap + low power” matters more than matching laptop‑class performance.

Security vs. performance features

  • A minority sees the lack of aggressive speculative/OoO features in current RISC‑V chips as a security advantage post‑Spectre and would accept lower speed for simpler, more auditable CPUs.
  • Critics respond that most users and software vendors won’t sacrifice performance for such security benefits.

Open ISA, ideology, and limits

  • Enthusiasts frame RISC‑V as enabling open cores, easier university–industry collaboration, and reduced license fees, potentially lowering fixed design costs and fostering shared IP.
  • Skeptics counter that open ISAs don’t solve fabrication, radio regulation, firmware lockdown, or binary‑blob GPU/baseband issues; many “openness” dreams remain constrained by economics and physics.

Software optimization and quirks

  • RISC‑V currently has less hand‑written assembly and tuning than x86/Arm in major projects (e.g., Go, ffmpeg), so some workloads are slower purely due to software maturity.
  • Some ISA “quirks” (e.g., sign‑extended 32‑bit values in 64‑bit registers, misaligned access behavior) are seen as pragmatic design tradeoffs by some and as tech‑debt‑like hassles by others.