TSMC 2nm Process Disclosure – How Does It Measure Up?

Ambiguous PPA Claims and Questionable Graphs

• Several commenters find the paper “frustratingly marketing‑like”: mostly relative numbers, minimal hard data, and graphs that look like commercials.
• A key TSMC scaling graph is called out as spurious: reverse‑engineering the bars shows ~55% improvement from N3 to N2 where public statements suggest ~30%; this mismatch may explain why the graph was apparently removed.
• Some see this as part of a broader trend: IEDM papers from TSMC being more marketing than technical, with missing pitches, SRAM cell sizes, and absolute numbers.

Node Naming and Diminishing Returns

• The “2nm” label is widely treated as pure marketing; commenters note that the numerical naming convention (dividing by √2 each generation) breaks down below 2nm.
• There’s frustration that “3nm to 2nm” suggests a big geometric shrink but real gains (30% power / 15% perf / modest density) are incremental.

Intel 18A vs TSMC N2

• Intel’s 18A is viewed as a “2nm‑class” competitor emphasizing performance over density, continuing Intel’s historical bias.
• Some recall Intel’s past schedule slips (10nm) and are skeptical of 2025–2026 HVM timelines, though others repeat the official roadmap.
• Debate exists on whether 18A is “literally” TSMC 3nm plus backside power; others argue process differences are substantial.

Value of 2nm: Who Needs It?

• For hyperscale datacenters, power and cooling dominate TCO; modest efficiency gains can justify very high chip prices, while inefficient parts become unsellable.
• Apple is cited as a customer that pre‑funds new nodes and insists on leading edge, puzzling some but praised by users for battery life and performance.
• Commenters stress you need either huge volumes or Nvidia‑like margins to justify 2nm NRE.

Power vs Performance Tradeoffs

• Some argue post‑Dennard, power efficiency is “king” because it ultimately gates usable performance.
• Others push back: foundries still offer both high‑performance and high‑density cell libraries; products mix them differently, showing the performance/power tradeoff still matters.

Design Cost and RISC‑V

• One comment claims 3nm design NRE exceeds $500M; another counters with an analysis suggesting $50–75M instead, highlighting disagreement.
• Multiple participants argue RISC‑V doesn’t “need” 2nm; current cores are far behind ARM/x86 in microarchitectural sophistication, not limited by node.
• Discussion centers on how performance mostly comes from predictors, caches, pipelines, etc., which are expensive, IP‑heavy, and tied to specific vendors.
• Ideas surface around “GPL‑for‑hardware” style licenses and open, high‑performance core releases to bootstrap an open hardware ecosystem.

Edge Devices and Node vs Design

• A side thread explores Raspberry Pi and Jetson power use for wildlife/object‑detection workloads.
• Current Pi (16nm) is seen as far from needing 2nm; commenters note manufacturing node isn’t everything—SoC design and software optimization often matter more for power.
• Jetson examples (20nm Nano, newer 4/8nm Orin) illustrate that big efficiency differences can arise on relatively similar or older nodes.

Nvidia Blackwell on 4N, Not 3N

• People ask why Blackwell stayed on 4N when 3nm is “in full production.”
• Suggested reasons:
  • Very large die (~750 mm²) are far more yield‑sensitive; cutting‑edge nodes are optimized first for small mobile SoCs.
  • Critical IP (SerDes, HBM PHY, special SRAM/CAM) often lags on new nodes, as early adopters don’t need it.
  • Using 4N allows higher yields and margins, with performance gains driven more by architecture and higher TDP than by lithography.
• There is some back‑and‑forth about how mature N3 really is for larger non‑mobile parts and the extent to which Apple’s big SoCs show yields are acceptable.

Slowing Scaling and Expectations

• Some see the weaker node‑to‑node gains and marketing spin as evidence the “era of easy VLSI scaling is over,” with society still demanding exponential progress.
• Others emphasize that scaling continues, just at higher cost and smaller incremental PPA steps; ASML’s CEO is cited as still seeing a multi‑node roadmap, but on a slower cadence.

Why Fabs in Arizona?

• Explanations include:
  • Historical semiconductor presence (Motorola, Intel, others) and existing talent/supply chains.
  • Stable geology and climate, plus designated industrial water from local projects.
  • Favorable tax policy and politics, especially in the context of U.S. industrial policy.
• Some question Arizona’s water suitability, noting fabs use huge amounts of water and recycling is energy‑intensive and partial rather than total.