Europe bets once again on RISC-V for supercomputing

Original Article ↗ Hacker News Discussion ↗

Grassroots Ecosystem and Developer Access

  • Many argue that supercomputing success requires a broad RISC‑V ecosystem first: cheap, hobbyist‑friendly boards (Pi‑like SBCs, mini‑ITX, laptops, school deployments) so enthusiasts can port and optimize software.
  • Several existing boards are cited (Orange Pi RV2, BananaPi BPI‑F3, Milk‑V, SiFive, BeagleV, Framework RISC‑V mainboard), but software support is described as patchy or SDK‑only; Debian support is noted as relatively strong.
  • Some suggest starting in VMs/emulators (e.g., QEMU) to get compilers and tooling ready, mirroring how processor design often proceeds.

RISC‑V vs ARM and Sovereignty

  • ARM is seen as technologically mature with broad software support and existing EU use in supercomputers, but also as licensed, litigious, and ultimately controlled via SoftBank and US‑linked capital.
  • RISC‑V is valued for being an open ISA with permissive licensing, reducing dependence on any single company or jurisdiction and avoiding future licensing shocks.
  • Several commenters stress European tech sovereignty and freedom from US export controls; others note ARM is British/Japanese and question how real the sovereignty risk is.
  • Some point out that ISA differences are minor compared to ecosystem, tooling, and vendor behavior.

China, Geopolitics, and Cooperation

  • China’s national RISC‑V push is seen as both an opportunity for collaboration and a strategic risk.
  • One view: EU and China share an interest in escaping US tech leverage, and limited technical cooperation on open RISC‑V could be pragmatic.
  • Opposing view: deepening dependence on an authoritarian China (already close to Russia) will be regretted; Europe should aim for minimal dependence on both US and China.
  • Broader political debate erupts about democracy vs authoritarianism, US unpredictability vs Chinese “stability,” and what alliances Europe should seek.

Technical and HPC‑Specific Discussion

  • For HPC, commenters emphasize that RISC‑V Vector (RVV) support is critical; current affordable RVV cores are in‑order and seen as a stepping stone to needed out‑of‑order designs.
  • Detailed questions are raised about RVV performance characteristics (LMUL choices, vsetvli overhead, gathers/compresses, segmented loads) and the need for real silicon, not just emulation, to tune compilers and libraries.
  • Slides and reports from EU projects show an ambitious design with out‑of‑order scalar cores plus very wide vector units (e.g., 16,384‑bit vectors, many lanes, HBM), indicating serious architectural work underway.

Funding Scale, Industrial Policy, and Feasibility

  • The €240M budget over six years is widely criticized as far too small—“two zeros short”—compared to US startups raising billions for accelerators.
  • Fragmenting money across 38 partners is seen as diluting impact; some suspect these projects function more as industrial subsidies or jobs programs than as globally competitive efforts.
  • Others note European fiscal constraints, fragmented funding mechanisms, cautious investment culture, and lack of local “anchor customers” (e.g., big AI chip buyers) as structural obstacles.

Practicality, Performance, and Dependency Concerns

  • Some are skeptical because current RISC‑V CPUs lag even cheap x86/ARM boards; they question when this will materially pay off.
  • There is pessimism that, despite “sovereignty” rhetoric, Europe may end up importing Chinese RISC‑V chips anyway, inheriting potential backdoor and supply‑chain risks.
  • A few suggest also pushing RISC‑V into general government desktops to reduce Windows/x86 dependence, but acknowledge retraining and software inertia (Microsoft‑centric education) as barriers.