The FPGA turns 40

Economics and Use Cases

• FPGAs are structurally “too expensive at scale”: once a product sells in large volume, an ASIC almost always wins on cost, power, and performance per watt.
• Despite that, FPGAs remain attractive where: volumes are modest, standards evolve (e.g., wireless base stations), respins are risky/slow, or upgrades in the field are critical (network gear, SDR, broadcast, HSMs, military).
• Several comments note huge list prices (even 6-figure parts) but emphasize that real-volume pricing is dramatically lower; FPGA vendor pricing models are described as opaque and extreme.
• There is disagreement on the continued relevance of “FPGA-to-ASIC” conversion services: some say they still exist (e.g., eASIC), others say major programs were discontinued or were never true ASIC.

Tooling, Languages, and Open Source

• Toolchains are widely criticized: proprietary, brittle, slow, non-reproducible without seed control, and locked behind opaque P&R heuristics for NP-hard problems.
• SystemVerilog dominates but is seen as messy and non-deterministic; VHDL is more deterministic but also disliked. “Easy” FPGA programming (HLS, LabVIEW-style flows) is viewed as perpetually promised but limited.
• Some report good experiences with open-source stacks (Yosys, nextpnr, OpenXC7, F4PGA) and note they drive sales for Lattice, which is considered comparatively open-friendly. Others argue reverse‑engineered toolchains are still too fragile for serious commercial use.

Performance, Architecture, and Comparison to GPUs/ASICs

• For acceleration, many say GPUs have “eaten FPGAs’ lunch” for most throughput-heavy workloads; FPGAs shine mainly in deterministic, ultra–low-latency I/O and streaming pipelines (radio, telecom, packet processing).
• There’s disagreement on performance gaps: one side quotes ~4–5× slower clocks; another cites research showing ~18× slowdown vs ASIC for a RISC‑V core.
• Lack of abundant, fast floating-point on mainstream FPGAs is seen as a major barrier outside AI/vision niches; fixed‑point retargeting is described as high-effort and error‑prone.

Dynamic / General-Purpose Reconfigurable Computing

• Several participants are enthusiastic about the long-standing vision of OS-like systems that swap FPGA circuits per task, but note that partial reconfiguration tools are poor and past efforts largely stalled.
• Cloud providers reportedly started with FPGAs (e.g., smart NICs) but are said to be moving toward “smart ASICs” with limited programmability.

AI and Future Directions

• Some speculate FPGAs (or CGRAs) could resurge once models can “directly” produce bitstreams; others are skeptical since P&R is NP-complete and not a language task.
• Consensus: LLMs are already useful for generating HDL/HLS scaffolding, but full bitstream generation will still require classical EDA flows for the foreseeable future.