GlobalFoundries to Acquire MIPS

Original Article ↗ Hacker News Discussion ↗

Strategic implications of GF acquiring MIPS

  • Seen as a move toward owning more of the stack: CPU IP + GF’s own fabs and packaging, especially attractive for embedded and low-end SoCs.
  • Some speculate GF could loss-lead in the low-end to gain share, now that they have both process and CPU IP in-house.
  • Others note GF’s processes are “old” in leading-edge terms, but still very relevant for the majority of chips (28–65nm and above), where most volume and the automotive/embedded markets sit.

State of MIPS and its shift to RISC‑V

  • Several comments say MIPS never delivered a modern high‑end core comparable to Alibaba’s XuanTie 910; recent billions of shipped RISC‑V cores mostly weren’t MIPS designs.
  • MIPS’ current pitch is high‑performance RISC‑V cores reusing classic MIPS microarchitectural ideas, but commenters haven’t seen public silicon or independent benchmarks to validate the claims.
  • Skepticism about “no‑V” (no vector extension) in MIPS’ advertised RISC‑V cores; viewed as a red flag for high‑end performance.
  • Historically, MIPS once occupied a similar “anyone can implement the ISA” niche that RISC‑V now fills, but its licensing and legal posture are remembered as hostile.

RISC‑V IP ecosystem and consolidation

  • Question raised whether this signals early consolidation among the many RISC‑V IP vendors.
  • Mixed views on whether companies “pay for RISC‑V IP”:
    • Some insist serious chip makers pay heavily for proprietary core IP (design + verification) from vendors like Andes/SiFive.
    • Others point to open‑source cores (e.g., C910, BOOM) already used in commercial products as evidence that paid IP isn’t always necessary.
  • Noted that China produces a lot of RISC‑V IP to avoid foreign IP control and sanctions; one RISC‑V AI startup (Esperanto) has already wound down.

GlobalFoundries’ process roadmap and 7nm controversy

  • Sharp debate over GF’s 2018 decision to cancel 7nm:
    • One side calls it a disastrous, obviously short‑sighted move that took them off the leading edge permanently.
    • The other argues they likely couldn’t afford it or make it profitable, lacked customer commitment, and might never have had a working 7nm process at scale.
  • Context: GF licensed 14/12nm from Samsung, struggled to deliver on a 7nm commitment to IBM, and later settled litigation.
  • Some argue dropping leading‑edge R&D dooms GF to long, slow decline; others say focusing on mature nodes (e.g., 28nm SOI, automotive/analog) is a defensible niche.

Architecture nostalgia: MIPS, delay slots, and RISC history

  • Several deep technical subthreads on:
    • MIPS delay slots and load delay slots, their original rationale, and why they became a liability for more advanced pipelines and virtual memory fault handling.
    • Comparisons with SPARC, PA‑RISC, Itanium, SuperH, register windows, and VLIW/EPIC failures.
  • MIPS is characterized by some as a “mipsed opportunity”: if it had truly been open and better managed, RISC‑V might never have been needed.

Meta: leading‑zero years

  • Long digression about one commenter’s habit of writing years with a leading zero (inspired by the Long Now Foundation).
  • Reactions range from amused and supportive to highly irritated; some find it distracts from otherwise valuable technical contributions.