TSMC to start building four new plants with 1.4nm technology

Original Article ↗ Hacker News Discussion ↗

Location, Arizona build-out, and geopolitics

  • Commenters note TSMC’s pattern: build the newest node in Taiwan first, then replicate abroad (e.g., Arizona), both for business (talent, suppliers) and geopolitical leverage.
  • Some see domestic 1.4nm fabs as reinforcing Taiwan’s “silicon shield” by keeping the most advanced capacity on the island, even as ~30% of advanced capacity is planned for Arizona.
  • Others argue business and geopolitics are inseparable: siting too much cutting-edge capacity in the US could make those fabs vulnerable to seizure if Taiwan fell.
  • Water usage in Arizona is raised as a concern; some argue fab water is highly recyclable, others counter that without regulation it’s cheaper to draw fresh municipal water.

What 1.4nm brings vs 4nm

  • Ignoring power, participants expect: higher transistor density → more cores, cache, and on-device compute, especially valuable for data centers and AI accelerators.
  • Several note that for smartphones, CPU performance is already “overkill,” so gains likely go into either longer battery life or more complex features rather than visibly new capabilities.
  • There’s disagreement on how much node shrinks still improve power; some say density is now the main benefit, others insist power/heat reductions remain central, especially for mobile and VR.

Costs, yields, and Moore’s Law

  • Multiple comments claim cost per transistor stopped falling around 28nm or early-2020s nodes; others challenge this and argue scaling continues, but not as cleanly.
  • People stress that newer nodes are more expensive initially, with enormous fixed design and mask costs; mature older nodes can be cheaper per useful transistor.
  • Chiplet architectures mixing old and new nodes are cited as a way to manage cost and yield.
  • Long back-and-forth debates whether continued transistor-count growth is driven mainly by die size increases versus genuine density improvements.

Physical limits and the meaning of “1.4nm”

  • Several clarify that “1.4nm” is now a marketing node name, not the literal gate length; actual transistor dimensions have changed modestly in the last decade.
  • There’s broad agreement that physics (e.g., quantum tunneling) poses eventual limits, but today’s bottlenecks are more engineering and economics than hard physical barriers.
  • One technical summary (from external reporting quoted in-thread) says TSMC’s 1.4nm “A14” node uses 2nd-gen GAAFET nanosheets and promises:
    • ~10–15% performance gain at same power, or
    • ~25–30% lower power at same performance, plus
    • ~20–23% higher transistor density vs N2.
  • Commenters emphasize this is an either/or tradeoff, not simultaneous gains.

SRAM and memory scaling

  • Some worry that as logic transistors continue to scale, SRAM does not shrink as well, so caches dominate die area.
  • Possible responses mentioned: less SRAM per core, or moving last-level caches to denser but slower eDRAM.
  • NAND and DRAM roadmaps are seen as more stagnant, with no dramatic breakthroughs visible in the thread.

US semiconductor industry, wages, and regulation

  • Several lament the perceived decline of US leading-edge manufacturing, blaming:
    • Financialization (buybacks instead of fab investment),
    • Risk-averse corporate culture,
    • High labor and compliance costs.
  • Others push back, noting there are still many US fabs, and modern fabs in the US can be relatively clean and locally welcome.
  • High US software salaries are seen as drawing talent away from hardware and manufacturing, while Taiwan’s lower wages and more focused talent pipeline support TSMC’s competitiveness.

China, Taiwan, and strategic risk

  • Some argue the US is encouraging offshore capacity to reduce dependence on defending Taiwan; Taiwanese interests favor keeping the island indispensable.
  • There’s extensive debate on China’s progress:
    • One side: China is still years behind, struggling with high-cost, low-yield nodes using DUV multipatterning, and unlikely to “leapfrog” EUV toolmakers soon.
    • Other side: rapid Chinese advances (e.g., shipping 7nm-class products, pushing toward 5nm) plus massive state investment could reach near-parity within a few years.
  • Industrial espionage and reverse engineering are mentioned as real factors, but others emphasize that replicating EUV-class tooling is extraordinarily hard, not just a matter of “stealing blueprints.”
  • Some discussion speculates on war scenarios: whether fabs would be destroyed or sabotaged, rumors of self-destruct or “kill switch” capabilities, and whether China would prefer capturing versus eliminating Taiwan’s fabs.

Role of AI demand and future outlook

  • One commenter attributes continued aggressive investment in new nodes largely to AI demand; they note that, e.g., moving from a 3nm to a 1.4nm-class SoC could roughly halve energy for similar performance.
  • Others don’t directly dispute AI’s role but don’t focus on it; overall sentiment is that leading-edge scaling continues, but with slower, more incremental gains and rising complexity and cost.