A CT scanner reveals surprises inside the 386 processor's ceramic package

Original Article ↗ Hacker News Discussion ↗

CT scanning technique and parameters

  • The chip’s lid was removed to improve scan quality; leaving it intact likely wouldn’t damage the CPU, but this wasn’t formally verified.
  • Industrial CT system used: Lumafield Neptune microfocus. Scan at ~130 kV, 123 µA, 1200 projections × 60s (≈21 hours).
  • Voxel size was 12.8 µm, with the scanner capable of 3–6 µm on smaller parts.
  • Compared to medical CT (~0.5–1 mm voxels and much shorter exposures), industrial scans use far higher dose and longer time to avoid artifacts and gain resolution.

Bond wires, shock, and reliability

  • Bond wires are suspended in air; some wondered if dropping a chip could bend them and cause shorts.
  • One view: any shock strong enough to meaningfully bend wires would likely shatter the ceramic first.
  • Others note that at “thousands of g” shock, wire bending and shorting is a known failure mode, with published research and real-world artillery-telemetry failures; orientation (chips facing down) can mitigate it.
  • Bonding is done via automated bonding machines, typically using ultrasonic friction welding; manual bonding persists mainly in research.

Hidden/NC pins, test modes, and Cyrix hacks

  • Discussion of undocumented “ICE mode” on 286/386: a hardware pin and/or special opcodes can drop the CPU into an in-circuit emulation/debug state, disconnecting it from the bus.
  • The article’s surprise bonded “NC” pad sparks speculation; consensus is it wasn’t a bond added then blown, since no remnants are visible.
  • Cyrix 486DLC reused seven of the 386’s NC pins for cache control, debug, power management, etc.; irony noted that the one NC Intel actually wired is an output, while Cyrix wants that same location as an input for cache enable.

Bus signals, addresses, and motherboard routing

  • Absence of A0/A1 is explained: 386 addresses 32-bit words and uses four Byte Enable signals (BE0#–BE3#) to select bytes/halfwords.
  • This swaps two address pins for four BE pins but also encodes transfer size, making it roughly pin-neutral and easing system design.
  • Some doubt that pinout was optimized much for motherboard routing; it appears more driven by internal package constraints.

Thermal/mechanical fatigue and museum systems

  • One contributor recalls detailed modeling and testing of thermo-mechanical cyclic fatigue in later packages; outcome was that it’s usually not a big issue—but daily power cycling of museum PCs is still discouraged.
  • Proposals to keep chips at constant temperature via external heaters face pushback: the whole PC still experiences warm-up, and very tight control would be required.

Website access, blocking, and ethics

  • A Russian reader reports the article is inaccessible; others suggest causes ranging from ISP/government DPI boxes to prior geo-blocking by the author.
  • Several note they block traffic from certain countries (Russia, China, Iran, etc.) due to high attack volume and low revenue, framing it as a pragmatic business or security decision.
  • Others criticize broad country blocks as unfair to individuals and of questionable ethical value in the context of geopolitical conflicts.

Packaging technology, economics, and aesthetics

  • Readers appreciate having hybrid/ceramic packaging visuals and explanations made public; this niche area lacks general educational material.
  • Old ceramic packages are widely praised as “peak” chip aesthetics; the CT “signals” layer is seen as poster-worthy and even suitable as a period “Intel Inside” motif.
  • Historical anecdotes discuss early reluctance to exceed 16 pins due to packaging cost and existing 16-pin infrastructure, especially when Intel was still primarily a memory company.
  • High US packaging costs vs. cheaper overseas lead-frame production are mentioned as a driver of change.

PC nostalgia and bus archaeology

  • Many reminisce about their first 386/486 machines: minimal cooling, small RAM and disks, and add-in cards for video and serial ports.
  • Confusion over whether early systems used AGP leads to clarifications: 386-era systems would have ISA and possibly EISA or early proprietary local buses; VESA Local Bus and later AGP appear with 486/Pentium-class boards.

Site UX and minor technical notes

  • One commenter suggests adding <label> elements to the layer-selection radios so labels are clickable; the author promptly updates the page. Others note nesting <input> inside <label> as a simpler approach.
  • Small technical nitpicks appear, such as whether “exponential” vs. “quadratic” better describes pin-count growth; clarification points to empirical exponential trends (e.g., Rent’s rule).