AMD's Ryzen 9 9950X3D2 Dual Edition crams 208MB of cache into a single chip

Original Article ↗ Hacker News Discussion ↗

AMD’s new Ryzen 9 9950X3D2 “Dual Edition” CPU packs 208 MB of on-chip cache by stacking 3D V‑Cache on both of its compute dies, prompting analysis of how this architecture affects real‑world performance. Commenters note that gains are highly workload‑dependent—substantial for cache‑sensitive tasks like some simulations and trading systems, but modest for many gaming or general workloads—and explore exotic ideas like running entire OSes effectively from cache. The launch also highlights broader market pressures: soaring DDR5 and SSD prices, finicky multi‑DIMM configurations on AM5, and the resulting hesitation to adopt new high‑end platforms despite impressive silicon.

Architecture and Cache Layout

  • 9950X3D2 has two compute dies (CCDs), each with its own L3 plus stacked 3D V-Cache; total 192MB L3 + 16MB L2 = 208MB advertised cache.
  • Each CCD’s L3 (32MB base + 64MB stacked) behaves as a unified 96MB L3 with slightly higher latency than smaller L3 configs.
  • L3 is local per CCD; coherency across CCDs goes via the IO die. There is no single shared L3 pool across both CCDs.
  • Extra cache on both CCDs avoids the “hybrid” X3D setup where only one CCD has large cache and requires special scheduling.

Performance Impact and Workloads

  • Strong disagreement on value: some argue extra cache beyond existing X3D adds little (~few percent); others report large gains for cache-sensitive workloads (CFD, FEA, finance/trading, some AI).
  • Benefits highly workload-dependent: memory-bound, synchronization-heavy, and “slowest-thread-matters” workloads may gain a lot when both CCDs have large L3.
  • For pure gaming, many feel the 9850X3D is a better value; AMD’s scheduler already prefers the cache-rich CCD on prior X3D parts.

L3 Locality, Cross-CCD Effects, and NUMA-Like Behavior

  • L3 is not globally shared; cross-CCD accesses incur extra latency and typically go through memory, though exact details of pulling clean lines between CCDs are described as unclear.
  • Datasets active on both CCDs tend to be duplicated in both L3s; an idle CCD cannot simply act as an L4 cache.
  • Equal-sized L3s on both CCDs should reduce contention and simplify scheduling versus mixed-cache designs.

DDR5 Prices, Platform Choices, and Stability

  • Many comments focus on the spike in DDR5 and SSD prices, with 64–128GB kits multiplying in cost since 2024–2025.
  • Some plan to delay AM5 upgrades or stick with AM4/DDR4 or older Intel platforms; others are glad they bought large DDR5 kits early.
  • Multiple reports of poor experience with 4 DDR5 DIMMs on AM5: low stable speeds, multi-minute (even ~30 min) memory training, instability. Enabling “memory context restore” in BIOS helps but isn’t always default.
  • High memory costs mean RAM and storage can now represent the majority of system price, affecting upgrade calculus.

Cache-as-RAM and “OS in Cache” Thought Experiments

  • Discussion of using cache as RAM: firmware already does this in early boot phases (cache-as-RAM).
  • People speculate about booting systems (DOS, Windows 9x, tiny OSes) entirely from L3, but note cache eviction, associativity, and architectural constraints.
  • Running a real system with no external RAM is seen as conceptually possible but practically expensive and nonstandard.

Product Naming, Timing, and Market Positioning

  • Mixed views on “9950X3D2” naming; several find it logically meaningful (base model + 3D cache + “2” for dual-CCD cache).
  • Some suggest this SKU exists to monetize leftover cache dies and/or to block competing high-end Intel launches.
  • Many see it as a halo product: great for niche high-end workloads, overkill for typical desktop or gaming use.