I got almost all of my wishes granted with RP2350

Original Article ↗ Hacker News Discussion ↗

Raspberry Pi’s new RP2350 microcontroller, debuting on the $5 Pico 2 board, is being hailed as a major upgrade over the RP2040, adding dual Cortex‑M33 cores with FPU, optional dual RISC‑V cores, more RAM, improved PIO, PSRAM support, stronger security features, and 5 V‑tolerant GPIO. Commenters compare it favorably on price, flexibility, and documentation to popular STM32 and ESP32 parts, while noting trade‑offs such as modest power consumption improvements, lack of high‑speed USB, and continued use of micro‑USB on the official dev board. Many see the dual‑ISA design as a strategic step toward RISC‑V and a powerful platform for both hobby projects and industrial products, especially where custom I/O and soft peripherals are needed.

Core features and variants

  • Dual Cortex-M33F cores at 150 MHz (commonly overclocked to ~300 MHz in tests), optional dual Hazard3 RISC‑V cores at 150 MHz on the same die.
  • 520 KiB SRAM, optional 2 MB in‑package QSPI flash (RP2354), external PSRAM support, PIO v2 with 3 blocks / 12 state machines, improved DMA.
  • Pico 2 board: 4 MB QSPI flash, 5 V‑tolerant (some) GPIOs, security features (signed boot, TrustZone, TRNG, glitch detection), footprint‑compatible with Pico 1.
  • 4 ADC channels on base package, 8 on 80‑pin variant; still no DAC. Slight ADC improvement only.

ARM vs RISC‑V dual architecture

  • At boot, each of two “sockets” can be mapped to either M33 or Hazard3; mix‑and‑match (1 ARM + 1 RISC‑V) is possible, but only two cores active total.
  • Rationale discussed: sharing bus fabric and avoiding a larger, more power‑hungry crossbar; not area of cores themselves.
  • Seen as a way to de‑risk a potential long‑term transition toward RISC‑V and hedge against ARM licensing changes.
  • Thread warns: benchmarks would really be M33 vs Hazard3, not generic “ARM vs RISC‑V”.

I/O, high‑speed tricks, and PIO

  • PIO still a standout: many see it as beating traditional peripheral sets; others note it’s under‑served by vendor‑maintained “soft peripheral” libraries and third‑party RTOSes.
  • Existing community PIO implementations for CAN and RMII Ethernet; several people report heavy refactoring needed to make RMII robust and standards‑compliant.
  • New HSTX block (one‑way high‑speed serial, can drive DVI/TMDS) excites people for inexpensive video and FPGA links; regret it’s not bidirectional.

Power, analog, and 5 V tolerance

  • Power system more complex: on‑chip regulator mainly for 1.1 V core; separate 1.8–3.3 V I/O and 3.3 V analog/USB rails still needed.
  • GPIOs are 5.5 V‑tolerant only when properly powered at 3.3 V and only on specific digital‑only pins; analog‑capable pins are not 5 V‑tolerant.
  • Some praise lithium‑cell support; ultra‑low‑power / coin‑cell use still seen as weak, though idle power reportedly improved.

Security and secure boot

  • New secure boot with OTP keys, signed boot, and a redundancy coprocessor plus glitch detection; $10k bounty and external audits cited as signals of seriousness.
  • Still no on‑the‑fly external flash/PSRAM encryption like some ESP32/STM32 parts; running fully from internal SRAM is seen as limiting for larger firmware.

Comparisons to other MCUs

  • Frequently contrasted with STM32H7: RP2350 praised for price, documentation, PIO flexibility, and less painful errata; critics note H7 still wins on raw performance, caches, and “real” peripherals.
  • Some say low‑power and wireless needs still favor Espressif and Nordic; others see RP2350 as strong for high‑speed I/O and hobbyist/industrial control.

Boards, packaging, and connectors

  • Pico 2 keeps micro‑USB for backwards mechanical compatibility and cost; this draws heavy criticism from those who’ve moved to USB‑C only.
  • Third‑party boards (e.g., with USB‑C, PSRAM, larger flash) highlighted but are pricier.
  • QFN60/QFN80 only; some hobbyists dislike bottom‑pad GND and wish for TQFP, others say cheap hot‑plate/toaster reflow or dev‑board modules solve it.

Tooling, SDK, and ecosystem

  • Official C/C++ SDK updated; MicroPython support expected. GPIO 5 V‑tolerance details clarified in datasheet.
  • New Bazel‑based “Pigweed SDK” showcased; reactions mixed—some love Bazel’s hermetic builds, others strongly dislike Java/Bazel and see it as misaligned with typical embedded workflows.
  • Desire for official PIO “soft peripheral” library (CAN, SD/MMC, MII, Bluetooth HCI) and stronger Zephyr integration.

Use cases and demos

  • Enthusiasm for: motor control (FOC, sensorless with more ADCs), retrocomputing (RAM/ROM emulation, classic systems), higher‑end displays via DVI/HSTX, high‑speed RP2350–FPGA links, and even Quake‑class games with PSRAM.
  • Several report significant real‑product use of RP2040 already and see RP2350 as addressing major pain points (FPU, security, RAM, peripherals).