Ask HN: Why hasn't x86 caught up with Apple M series?
Instruction Set vs. Implementation
- Strong disagreement on whether ARM vs x86 ISA explains Apple’s lead.
- One camp: x86’s complex, variable-length decoding and historical baggage (x87, many SIMD extensions, 8 GP regs) impose real power and design costs.
- Other camp: all modern CPUs translate instructions to µops; decoder power is “a drop in the bucket” and implementation, not ISA, dominates.
- Multiple comments argue x86 decode power is non‑trivial (papers cited showing ~3–10% of package power, more of core power) and has worsened with wider decoders.
Core Design, Big.LITTLE, and Performance
- Apple’s performance cores are wide and efficient at moderate clocks; big.LITTLE is used for “race to sleep” and background work.
- Intel/AMD often push clocks near the inefficient end of the V/F curve to win benchmarks, increasing heat and reducing battery life.
- AMD’s Zen 5/5c and Intel’s recent cores narrow the gap, but commenters note Apple still leads in single‑thread perf/W in cross‑platform tests (SPEC, Cinebench).
Memory, SoC Integration, and Unified Designs
- Apple’s on‑package LPDDR (unified memory) and tightly integrated GPU/NPU are seen as a major advantage for bandwidth, latency hiding, and power.
- Similar ideas are appearing in x86 land (AMD Strix Halo / Ryzen AI Max, on‑package LPDDR, large caches, chiplets), but often with higher die sizes and worse efficiency.
OS, Power Management, and Software
- Many argue Apple’s real edge is vertical integration:
- macOS is heavily tuned for power (timer coalescing, App Nap–like behavior, aggressive background throttling, efficient Safari).
- iOS/iPhone heritage drove years of “race to sleep” engineering.
- Linux and Windows are criticized for:
- Poor or inconsistent idle and sleep behavior (Modern Standby, s0ix issues, systems waking in bags).
- Inefficient defaults, especially on laptops (missing GPU video decode, bad governors, background processes, security agents like EDR draining batteries).
- Some report Linux on M‑series (Asahi) is still noticeably worse than macOS on the same hardware, underscoring software’s role.
Framework / x86 Laptop Specifics
- Framework’s modularity, use of socketed DDR (vs LPDDR), and cooling constraints likely hurt efficiency compared to sealed designs.
- Users report that with tuning (powertop, TLP, udev rules, lower TDP modes, better browsers) Ryzen laptops can approach—but generally not match—MacBook battery/runtime under light workloads.
Competing Chips: Strix Halo, Lunar Lake, Snapdragon X Elite
- AMD Strix Halo / Ryzen AI Max:
- Praised as the closest x86 analogue (unified memory, strong MT, good iGPU), but multiple commenters point out significantly worse ST perf/W vs M4/M4 Pro and higher total power.
- Intel Lunar Lake:
- Shows that x86 can hit M‑class idle power with aggressive design, but overall efficiency and performance still trail; seen as a one‑off, expensive design.
- Snapdragon X Elite:
- ARM but not Apple; slower and less efficient under load than top x86, yet often with better battery life due to platform‑level power management.
Backward Compatibility and Market Incentives
- x86 vendors are constrained by decades of backward compatibility expectations (DOS era, 32‑bit code, legacy FP/SIMD), complicating design and software.
- Apple repeatedly cuts legacy (32‑bit, PPC, AArch32) and forces developer transitions, enabling cleaner hardware and OS evolution.
- Some argue Intel/AMD could attempt a “new clean x86 mode” or new ISA with emulation, but the ecosystem and business risk are huge.
User Experience and Subjective Reports
- Many developers report MacBook Pros (even M1/M2) feeling dramatically snappier, cooler, and quieter than high‑end x86 laptops for everyday dev workloads (Docker, IDEs, builds) with far longer usable battery life.
- Others counter that under sustained heavy loads (rendering, gaming, large LLMs or HPC) high‑power desktop x86 still dominates, and that price, repairability, expandability, and openness remain strong reasons to prefer x86 systems despite Apple’s efficiency lead.