AMD claims Arm ISA doesn't offer efficiency advantage over x86

Original Article ↗ Hacker News Discussion ↗

ISA vs Microarchitecture and Efficiency

  • Many comments agree with AMD’s claim: ISA (x86 vs ARM vs RISC‑V) is a minor factor for efficiency on large, out‑of‑order cores.
  • Performance and power are dominated by microarchitecture: branch prediction, memory hierarchy, cache sizes, uncore, power management, and process node.
  • Decode for x86 is more complex and uses more transistors, but several people cite data and industry interviews claiming it’s a small share of core power/area (~10% or less) and largely “solved” with uop caches and predecode.

Apple, Qualcomm, and x86 Perf/Watt

  • Multiple users point out that Apple’s M‑series and Snapdragon X regularly show better perf/W in laptops than Intel/AMD, even when process nodes are similar.
  • Counter‑arguments:
    • Apple buys leading TSMC nodes earlier and designs for efficiency, not max clocks.
    • x86 parts are often tuned for peak single‑thread performance; the last 10–20% of performance costs disproportionate power.
    • Battery life tests are mostly idle/bursty; OS and system power management dominate, not ISA.
  • Disagreement remains on how much of Apple’s lead is architecture vs process vs software; exact breakdown is unclear.

Instruction Decode and ISA Details

  • Long subthreads debate variable‑length x86 vs fixed‑length ARM/RISC‑V:
    • Some argue x86 decode is inherently wasteful and complex.
    • Others provide technical details showing width and throughput can match or exceed ARM, with predictors, predecode, uop caches, and compact addressing modes (e.g., lea, ModRM).
  • ARM’s weaker memory model is seen as a real but modest efficiency enabler; hard to isolate experimentally.

RISC‑V Critiques

  • Several developers describe RISC‑V as “academically clean but messy in practice”:
    • Misaligned access semantics, hard‑coded 4K pages, awkward LR/SC guarantees, entropy CSR issues, fragmented extensions and discovery mechanisms.
  • Despite warts, its open licensing and lack of IP lock are viewed as strategically important.

Software, OS, and Integration

  • Strong consensus that Apple’s vertical integration (SoC, RAM on package, PMIC, storage, macOS) is a huge contributor to user‑visible efficiency.
  • Other ARM laptops without such integration often have mediocre battery life, supporting the “implementation, not ISA” thesis.
  • Windows/Linux are seen as less aggressively optimized for low idle power and race‑to‑sleep.

Heterogeneous Cores and Legacy Instructions

  • Ideas about dropping legacy/x86 features on efficiency cores are generally seen as impractical:
    • OS schedulers and applications assume stable CPU features; mixed capability cores lead to SIGILL, migration complexity, and hard‑to‑debug behavior (cited in AVX‑512/E‑core history).

Boot and Platform Standardization

  • Beyond ISA, several criticize ARM/RISC‑V for fragmented, board‑specific boot flows versus the relatively uniform x86 BIOS/UEFI world.
  • Server‑oriented standards (ARM SBSA/SBBR, RISC‑V server platforms) exist, but coverage for consumer devices is still incomplete.