Samsung is expected to more than double output of its HBM4 and HBM4E DRAM
Samsung’s plan to more than double production of its high-bandwidth HBM4/HBM4E memory is seen as a direct response to insatiable AI and data center demand, but many fear it will starve conventional DDR4/DDR5 output and push consumer RAM prices even higher. Commenters debate whether classic supply‑and‑demand dynamics and new fabs will eventually bring a glut and cheaper memory, or whether past cartel behavior and cautious investment will keep prices elevated for years. The thread also delves into technical and geopolitical angles, from why HBM is so capacity- and yield-intensive to how U.S. export controls are forcing China to build its own HBM and chipmaking stack.
Impact on consumer DRAM and prices
- Many expect Samsung reallocating capacity toward HBM4/HBM4E (up to ~80% of output, per thread) to worsen shortages of standard DDR4/DDR5 and LPDDR.
- Several commenters note Micron’s claim that HBM capacity can be a ~3:1 tradeoff vs conventional DRAM bytes, amplifying the effect.
- Some argue overall fab capacity is also increasing and that high prices will eventually draw more supply and lower prices; others counter that expansions are slow (multi‑year) and current moves are mostly conversions to HBM, not new fabs.
- There is concern that consumer DRAM prices may stay high until ~2028+ and that DRAM makers have a history of cartel-like behavior.
Market dynamics and AI bubble risk
- AI demand is seen as “radioactive” and outbidding all other buyers; hyperscalers sign long‑term contracts and hoard HBM, SSDs, and GPUs.
- Some think an eventual AI bust will leave manufacturers with excess HBM, after which they can quickly revert lines to DDR and create a consumer glut.
- Others argue demand for LLMs and agents is still early, and that memory bandwidth remains a fundamental bottleneck, so a near‑term crash is doubtful.
HBM vs consumer memory (technical constraints)
- HBM is DRAM stacked with TSVs, offering huge bandwidth but worse capacity-per-wafer, higher packaging complexity, and usually higher latency.
- It must be co-packaged very close to the processor on an interposer; no DIMMs, making it unsuitable as drop‑in PC memory.
- Laptops and desktops currently favor DDR/LPDDR for latency, idle power, cost, and upgradability; unified memory on Macs is LPDDR, not HBM.
China, sanctions, and geopolitics
- Thread claims Chinese AI accelerator production is now bottlenecked by domestic HBM capacity and sanctions on advanced packaging tools.
- Huawei and CXMT reportedly face low HBM yields and shorter stacks; they compensate with more wafers, chiplets, and alternative memory architectures.
- Several argue sanctions are accelerating China’s push for semiconductor self‑sufficiency, though timelines and ultimate competitiveness are debated.
Manufacturing and yield challenges
- HBM consumes more wafer capacity because of TSV area, wide buses, tall stacks, and brutal packaging yields: one defect can waste an entire stack plus GPU die.
- Back‑end steps like die thinning and thermal compression bonding are highlighted as technically extreme but now industrialized at massive scale.