When teaching computer architecture, why are universities using obscure CPUs?

Original Article ↗ Hacker News Discussion ↗

Universities often teach computer architecture using outdated, simplified, or even fictional CPUs rather than x86 or ARM, prioritizing conceptual clarity over direct industry relevance. Commenters argue that minimal instruction sets make it feasible to go from transistors to working programs in a single semester, avoid vendor IP issues, and put all students on equal footing, while still providing a foundation that transfers to real-world ISAs like RISC‑V or ARM. Some criticize this approach as detached from practical needs, but others note that learning core principles once makes it easier to pick up any architecture later.

Pedagogical focus and simplicity

  • Intro architecture courses often go from transistors/logic gates up to simple programs in ~12 weeks.
  • Toy or simplified ISAs with small, regular instruction sets make it feasible to cover the whole stack (flip‑flops → registers → ISA → simple programs).
  • Modern CPUs (x86, ARM, etc.) have too many instructions and microarchitectural features (branch prediction, speculative execution, pipelines, complex encoding) to explain in the available time.
  • The goal is to teach core concepts that transfer to any ISA, not to train students as specialists in one architecture.

Benefits of “obscure” or fictional architectures

  • They avoid giving an advantage to students already familiar with a popular ISA; everyone starts from zero.
  • Removing historical baggage and oddities (segmentation, weird condition codes, special registers) lets courses focus on essentials.
  • Fictional ISAs (e.g., tiny 8–13‑instruction machines, MARIE, LEGv8, nand2tetris‑style CPUs) are small enough that students can implement simulators, assemblers, or even hardware.

Which architectures show up

  • Legacy real ISAs: MIPS, 68000, 8086/8088, 8051, 68HC11/12, VAX, SPARC, PowerPC, Z80, 6502.
  • Modern real ISAs: x86/x64 (in some assembly courses), ARM (often via Raspberry Pi or derived teaching subsets), RISC‑V (increasingly common).
  • Pure teaching ISAs: DLX, LEGv8, MARIE, custom 4‑bit/educational CPUs, Wirth’s RISC‑5, exam‑driven ISAs like COMP‑X/CAP‑X.

RISC‑V, ARM, and IP issues

  • RISC‑V is praised as MIPS‑like but cleaner, with a very small core (≈40–50 instructions) and no patent/licensing barriers.
  • ARM is seen as a good practical target but reportedly has IP/licensing frictions that pushed at least some curricula and textbooks toward RISC‑V.
  • Some expect RISC‑V to become both a teaching ISA and a marketable skill.

Debate over practicality and x86

  • Many argue x86/x64 is a “convoluted mess” and a poor first ISA; better suited as an advanced “how not to design an ISA” case.
  • Others report successful x86/8086‑based courses and note that a restricted subset is teachable and still relevant.
  • Broader tension: some insist universities should prioritize timeless concepts over corporate training; others counter that degrees are de facto job preparation and should connect to real industry architectures.