IBM debuts sub-1 nanometer chip technology

Original Article ↗ Hacker News Discussion ↗

IBM’s Business Model and Commercialization

  • Consensus that IBM no longer runs volume production fabs; it operates R&D fabs and licenses process technology.
  • Examples cited: past licensing of 2 nm to Rapidus and fabrication of IBM-designed CPUs by Samsung.
  • Revenue seen as coming from IP licensing, technology transfers, and support for partners who deploy ASML tools and IBM-developed processes.
  • Some view this as a successful “pure R&D + IP” model; others see it as a sad downsizing from IBM’s historic manufacturing role.
  • IBM’s roadmap suggests possible production use of this node in ~5 years, but commenters note that implies significant remaining challenges.

R&D Fabs, ASML, and Government Links

  • Albany, NY facility described as a heavily subsidized, advanced R&D fab where ASML brings up prototype (including High-NA EUV) tools with IBM’s help.
  • Cymer is mentioned as the EUV light source provider; Zeiss optics as key for High-NA EUV.
  • US CHIPS Act and state funding reportedly tied to keeping core EUV R&D and prototyping in the US and influencing ASML export decisions.

“Sub-1 nm” Node Naming and Marketing Skepticism

  • Strong pushback that nothing on-die is physically 0.7 nm; micrographs show features in the ~5–10 nm range.
  • Explanation offered: “0.7 nm” is an equivalent planar node label based on transistor density vs older planar processes, not a real dimension.
  • Many argue node names became marketing terms decades ago and now mostly signify relative generation and PPA (power, performance, area), not geometry.
  • Others call this deceptive “nm theater” and suggest regulators could eventually step in, though that’s seen as unlikely.

Density Metrics and 3D Structures

  • Several commenters advocate for clearer metrics: transistors/mm², NAND-gates per area, or even per volume (for true 3D integration).
  • Counterpoint: current logic processes still have a single active device layer; 3D terms (FinFET, GAA, “nanostack”) refer to device shape, not stacked logic layers like 3D NAND.
  • Industry reluctance to adopt density-based naming is attributed to marketing flexibility and cross-foundry comparability issues.

Physical Limits and Future Scaling

  • Discussion of fundamental limits: gate lengths in silicon estimated to bottom out around 10–15 nm due to tunneling and leakage.
  • Quantum effects already problematic at a few-atom gate thickness; some think we hit hard limits in the 2030s absent radically new materials or architectures.
  • Ideas like wafer stacking, “logic folding,” and better 3D integration are floated, but commenters stress huge yield, alignment, and thermal challenges; commercial viability remains unclear.

IBM’s Role and Reputation

  • Many highlight IBM’s long history of key innovations (interconnects, density advances) and ongoing high patent output.
  • Others criticize what they see as overhyped marketing (e.g., Watson, node naming) and question how much of IBM Research translates into broadly visible products.
  • Still, IBM hardware (POWER, z) is said to underpin large fractions of enterprise and financial backends, even if end users rarely see it directly.