PCIe 7.0 Draft 0.5 Spec: 512 GB/s over PCIe x16 On Track For 2025

Original Article ↗ Hacker News Discussion ↗

PCIe 7.0 aims to deliver up to 512 GB/s over a x16 slot by doubling signaling rates while retaining the same connector and much of the PCIe 6.0 physical-layer design, raising questions about how far high-speed serial links can be pushed without new form factors. Commenters contrast this rapid bandwidth scaling with the relative stagnation of CPU clock speeds, pointing to advances in SerDes, encoding, materials, and analog design, but also note trade-offs in power, cost, latency and signal integrity that may require cables or stricter board layouts. Much of the interest centers on implications for GPUs, SSDs, CXL-based memory expansion, and AI workloads, with some arguing that consumer use cases are already over-served while data centers and HPC clusters are hungry for every extra gigabyte per second.

How PCIe Keeps Doubling Bandwidth

  • PCIe 7.0 mainly doubles the physical-layer frequency relative to PCIe 5.0/6.0 while reusing PAM4 signaling, FLIT encoding, and FEC from 6.0.
  • Earlier generations gained bandwidth via better encoding (8b/10b → 128b/130b) and stricter board materials/layouts.
  • Commenters note this is easier than doubling CPU clocks because PHYs are simpler than CPUs and occupy far less die area and power.
  • One view: signaling rates were historically far from their theoretical limits, while CPU clocks are closer to theirs.

Physical & Signaling Challenges

  • Higher speeds demand better PCB material, tighter signal integrity, equalization, and sometimes shorter trace lengths; some expect cables or mezzanine-style connectors at Gen 7.
  • Discussion touches on transistor size, voltage swing, fanout, and pipeline depth; serial links can be implemented with relatively small, fast SERDES blocks compared to full CPUs.

Consumer Platforms, Lanes, and Real-World Need

  • Many consumer boards expose only one true x16 slot; others are electrically x4 or x8 and share lanes.
  • Some blame CPU vendors’ lane limits and market segmentation; others note real packaging and die-cost constraints.
  • Several argue typical consumer workloads (gaming, dev work) rarely saturate PCIe 4.0/5.0, so the main benefit is more devices per lane, not per-device speed.
  • Others counter that history shows software and workloads (especially ML and games) will eventually absorb new bandwidth.

PCIe vs NVLink and Other Interconnects

  • NVLink bandwidth (especially upcoming versions) remains far ahead per GPU, though marketing differences (per-direction vs bidirectional figures) cause confusion.
  • Even with 7.0, a x16 PCIe link sits between older and mid-generation NVLink versions in bandwidth.
  • NVLink trades off stricter latency requirements for higher bandwidth density; PCIe must work across many vendors and cheaper platforms.

PCIe as Memory, CXL, and GPU Access to RAM

  • Multiple comments stress latency, not bandwidth, as the main reason PCIe is unsuitable as a primary memory bus.
  • Rough consensus: DRAM access is tens of nanoseconds, PCIe is hundreds of nanoseconds to microseconds, though exact ratios are disputed.
  • CXL is mentioned as bringing coherency and lower latency on top of PCIe, useful for accelerators and memory expansion, but still notably slower than local DDR.
  • For large ML models, better PCIe/CXL helps, but future models and HBM bandwidth likely outpace these gains.

Switches, Topology, and Ecosystem

  • There is demand for PCIe switches that trade a few fast lanes for many slower/wider ones to support legacy NICs, HBAs, and multiple NVMe devices.
  • PCIe switches exist but are often expensive or targeted at enterprise; consumer boards rarely integrate them due to cost.

Timeline, Power, and Cost Concerns

  • PCIe generations take years between draft, final spec, platform support, and real devices; 7.0 is expected to follow a similar trajectory.
  • Some worry each doubling may come with higher power, tighter tolerances, and cost, questioning whether this is an efficiency gain or just “more with more.”
  • Others see it as necessary progress for HPC, disaggregated memory, and large GPU clusters, even if average consumers lag several generations behind.