Chinese researchers planning 1,600-core chips that use an entire wafer
Chinese researchers are exploring wafer-scale chips with around 1,600 cores, similar in concept to Cerebras’ massive AI processors that use an entire silicon wafer instead of individual dies. Commenters weigh technical hurdles such as defect tolerance, power delivery, routing, and extreme cooling requirements, while noting that earlier wafer-scale efforts date back decades and that Cerebras has already demonstrated a practical implementation. The conversation also touches on China’s economic and industrial prospects, including whether its hardware advances will be matched by robust software ecosystems and sustained investment.
Wafer-scale concept and yield management
- Commenters note wafer-scale integration is an old idea, now made practical by examples like Cerebras.
- Concern: low yields and defects across such large dies. Discussion centers on designing in redundancy (extra cores, links) and using fuses or post-fab repair to disable bad regions.
- Some suggest relaxing design rules for critical routing/supervisory logic to improve yield.
- A side question arises on how foundries like TSMC bill for poor yields; this remains unanswered in the thread.
Routing, heterogeneity, and reliability
- Key risk: defects in network blocks or cores that sit on routing paths can create irregular latencies and bandwidth.
- Some argue existing CPUs already have heterogeneous core-to-core latency and software mostly ignores it.
- Others worry that large, irregular topologies make performance unpredictable, though Cerebras is cited as a proof that robust routing around faults is possible.
Cooling and power delivery
- Heat removal is seen as a core challenge but not insurmountable.
- Proposed solutions: water-cooled copper blocks, immersion cooling, vapor phase change, and industry-scale radiators/pumps.
- Power delivery is highlighted as even more daunting than cooling, with tens of thousands of amps and complex mechanical interfaces.
- Several note that running many cores at lower voltage/clock speeds can keep total power manageable.
Process node, performance, and design tradeoffs
- The described Chinese design uses a 22 nm process, viewed as mature but far from cutting edge.
- Some speculate that older nodes might yield well enough to make wafer-scale viable, but what “near-100% yield” means is unclear.
- Discussion touches on trading frequency for area and using near-threshold voltage to limit power.
Historical precedents
- Past wafer-scale efforts are referenced: early 1980s/1990s projects, neuromorphic wafers, Inmos/transputer ideas, and failed commercial attempts.
- Lesson: packaging/cooling and economic viability have historically been the bottlenecks, not pure feasibility.
China, economics, and viability
- Thread diverges into debate about China’s macroeconomy: some claim mounting debt, deflation, and demographic issues limit long-term support for such projects; others argue “collapse” narratives are exaggerated or politically motivated.
- No consensus emerges; the economic outlook is portrayed as highly contested.
Software ecosystem and adoption
- Several emphasize that hardware success depends on software ecosystems and standards.
- Skeptics argue China has not yet built widely adopted software stacks around novel hardware, and non-standard architectures struggle without strong toolchains and user bases.
- Others counter that if such chips work and are accessible, software will follow, and that hardware remains the harder, more capital-intensive part.