RISC-V Is Inevitable: State of the Union Keynote Argues
RISC-V’s open, royalty-free instruction set is rapidly gaining ground in embedded systems and microcontrollers, and some see it as an eventual challenger to ARM in smartphones and general computing. Commenters highlight its appeal for cost-sensitive manufacturers, geopolitical hedging and custom chip design, but note serious hurdles: immature high-performance implementations, ISA fragmentation, and massive software and ecosystem inertia around ARM and x86. Related efforts like CHERI-based secure architectures spark interest for safety-critical use, yet face their own adoption and business-case challenges.
Perceived inevitability and likely markets
- Many see RISC‑V as “inevitable” in low‑margin and embedded markets because it is royalty‑free and legally simpler than ARM.
- Some compare it to Linux: not necessarily dominant everywhere, but a powerful, open default that companies converge on.
- Others push back: there is “nothing inevitable” in consumer markets dominated by Apple/x86/ARM, and software inertia is very strong.
Performance and efficiency
- Current general‑purpose RISC‑V SoCs are far behind top ARM/x86 in performance per watt; one estimate is ~1/6 efficiency.
- Fastest consumer‑reachable chips (e.g., SpacemiT K3/X60) are said to be usable for desktop tasks and entry‑level phones, but not competitive with high‑end ARM/x86.
- Some argue the ISA is not the main bottleneck; advanced memory controllers, interconnect IP, and cutting‑edge nodes are missing or expensive.
Ecosystem, fragmentation, and standards
- Concern that RISC‑V’s extension model and multiple profiles (e.g., RVA23) have led to ISA fragmentation and confusion about a “generic” RISC‑V target.
- Others point out RV64GC already has strong code density, disputing that “billions of extensions” are a serious problem.
- Software maturity is improving as more packages are built for new RVA23‑class chips, though often unoptimized.
Embedded, MCUs, and existing deployments
- RISC‑V is already common in deeply embedded microcontrollers and controller cores inside larger chips, displacing 8051, Xtensa, ARC, etc.
- Espressif has moved new ESP32 lines to RISC‑V; Western Digital and Nvidia are cited as shipping large volumes of embedded RISC‑V cores.
- Some embedded developers say ARM Cortex still overwhelmingly dominates MCUs, with RISC‑V mostly niche outside a few vendors.
Apple, ARM, and business considerations
- Discussion notes Apple’s long‑term, low‑per‑device ARM architecture license (into the 2040s) and strong in‑house ARM core capability.
- Several argue this makes a full ISA switch to RISC‑V unlikely unless ARM licensing terms change substantially.
- Others speculate on long time horizons (10–20 years) where RISC‑V’s ecosystem might become attractive, but acknowledge a costly migration and another compatibility break.
Security, CHERI, and Rust
- CHERI on RISC‑V is debated: technically promising for memory safety and fine‑grained compartmentalization, but seen by some as too invasive and niche.
- Some think Rust’s impact on memory‑safety bugs weakens CHERI’s business case; others counter that CHERI still benefits unsafe code and legacy C.
- Availability is an issue: research boards exist, but affordable mass‑market CHERI hardware does not, limiting grassroots experimentation.
Hardware and SIMD experimentation
- Developers interested in SIMD/RVV note few affordable RVV‑capable boards; suggestions include SpacemiT K3/X60 SBCs and Orange Pi RV2.
- Emulation via QEMU and Sail models is recommended for early work, but not for serious performance profiling.
Geopolitics and regulation
- Non‑US players (especially in China) are framed as strong RISC‑V drivers, both to avoid US‑controlled IP and licensing.
- Some warn US export controls could restrict use of Chinese RISC‑V chips, though others argue over‑restriction would hurt US interests.