A third world engineer responds to “RISC-V: They should have known better”

Original Article ↗ Hacker News Discussion ↗

RISC-V’s open instruction set is praised for enabling ultra-cheap microcontrollers and tools that are accessible even in countries where shipping and import costs make mainstream ARM parts effectively unaffordable. Critics, however, argue that the RISC-V ISA is technically flawed, overly fragmented, and unlikely to match ARM or x86 in high‑end performance or stable binary compatibility. Many commenters conclude that while RISC-V may not be the cleanest design, its zero licensing cost, flexibility for custom chips, and growing ecosystem make it economically and strategically compelling, especially outside traditional tech centers.

Article access and meta

  • The linked blog repeatedly rate-limited readers; many could only view it via multiple archive mirrors.
  • Some noted the irony of an “embedded engineer” site apparently not caching static HTML or handling modest traffic.
  • Separate meta-thread argued that Hacker News has become less Bay Area–centric and more European/DACH-influenced, though others strongly disagreed and see it as still very US/SV in mindset.

Cost, shipping, and “third world” constraints

  • A major discussion centers on how shipping and import friction dominate economics in places like Trinidad and Tobago and parts of Latin America/Africa.
  • Western distributors (Digi-Key, Mouser, etc.) have a steep “floor” shipping cost (e.g., ~$60 minimum) regardless of order size; this forces bulk buying.
  • At 10¢ per RISC‑V MCU vs $1+ for alternatives, teachers and hobbyists can afford to order and “burn” many more chips in experiments.
  • Freight forwarders and Chinese sellers (AliExpress, Temu) partially mitigate costs, but reliability, customs, and verification issues remain.
  • Several posters question or clarify claims about specific shipping costs to Nigeria/Bangladesh; international shipping routing and local tariffs make experiences vary widely.

RISC‑V vs ARM/x86: economics and IP

  • Many see RISC‑V’s core advantage as licensing freedom: no per-core IP fees, no need to “beg” ARM, fewer legal threats than x86/ARM for new entrants.
  • This openness enables niche chips (e.g., tiny MCUs, custom MMU-equipped cores) and “mostly open” secure SoCs that would be hard or impossible under ARM’s licensing.
  • RISC‑V is praised for enabling very cheap microcontrollers and low-cost Linux-capable boards that are accessible to students and engineers outside wealthy regions.
  • Critics respond that similarly cheap ARM and clone MCUs exist from Chinese vendors; RISC‑V’s advantage is not purely price but the long‑term ecosystem and legal safety.

Technical merits and shortcomings of RISC‑V

  • The original critical article focused on ISA design flaws: optional extensions, feature detection, interrupt handling, vector design, and concerns about fragmentation.
  • Some commenters agree: RISC‑V could have learned more from prior ISAs, especially for embedded and for clean feature discovery; vector masks and context switching are common targets.
  • Others counter that many complaints are “nitpicks”: with enough engineering, any ISA (including x86) can yield high performance; open toolchains and shared compilers are a major win.
  • There’s tension between “it could be technically better” and “it’s already economically better and good enough.”

High-end performance, fragmentation, and future outlook

  • Broad consensus: current off‑the‑shelf RISC‑V SBCs lag comparable ARM boards in performance and efficiency; often near Raspberry Pi 4/5 levels at best.
  • Some highlight emerging cores (e.g., commercial high‑end RISC‑V designs) claiming Zen‑ or M1‑class IPC, but these are mostly not yet shipping on cutting‑edge nodes; skepticism is common.
  • Fragmentation concerns: many optional extensions and vendor variations could complicate binary distribution, though some argue cloud/server ecosystems will naturally converge on de facto profiles.
  • Several posters predict that, as with x86 and later ARM, the cheapest, highest‑volume ISA tends to become the performance leader; others doubt RISC‑V will ever match x86/ARM investment at the very high end.

Language and framing

  • Some object to the term “third world,” preferring “Global South” or “developing,” while others note the original Cold War meaning differed from “poor.”
  • A few feel the response piece leans too hard into a moral/“privilege” framing rather than directly engaging the technical ISA critique; others see that socioeconomic lens as exactly what’s usually missing.