Intel puts 1nm process (10A) on the roadmap for 2027

Original Article ↗ Hacker News Discussion ↗

Intel’s roadmap now targets a “1 nm” (10 angstrom) manufacturing process by 2027, part of an aggressive plan to regain process leadership and build AI-focused, highly automated fabs. Commenters question both Intel’s ability to hit its timelines, given past 10 nm delays, and the meaning of node labels themselves, noting that “nm” and “Å” are now marketing terms loosely tied to density rather than any real 1 nm feature. The thread also touches on industry-wide pressures at the physical limits of silicon, the strategic importance of EUV and High-NA tools, and whether Intel’s foundry push can provide a credible alternative to TSMC and Samsung for advanced AI and server chips.

Intel’s Roadmap and Catch‑Up Prospects

  • Some argue Intel is closer to TSMC than headlines suggest: Intel 4 (“7nm” rebrand) is said to have density roughly comparable to TSMC “3nm”.
  • Others stress Intel 4/3 are transitional, with limited product use so far (Meteor Lake mobile, upcoming server parts) and that 20A/18A may slip; “five nodes in four years” is viewed by some as effectively only 2 real new nodes, already delayed by 1–2 quarters.
  • Optimists see recent execution as a recovery: new CEO era, big EUV/High‑NA orders, RibbonFET and PowerVia, and strong 18A foundry interest (many external design wins).
  • Skeptics doubt timelines and profitability, given past 10nm/14nm struggles and enormous fab complexity.

What “1nm / 10A” Actually Means

  • Broad agreement that node names (7nm, 3nm, 1nm, “A”) are marketing labels, not literal feature sizes.
  • Multiple comments share tables showing “1nm” nodes having ~40–50nm gate pitches and ~16–20nm metal pitches; nothing on chip is literally 1nm.
  • Some frame the label as a “transistor‑density equivalent” continuation of historical scaling; others say even that link has largely broken.
  • IEEE Spectrum’s “The Node is Nonsense” is cited as a good overview.

Physical Limits and Scaling Slowdown

  • Commenters note we are near atomic scales (e.g., silicon lattice spacing ≈0.5nm), but also that actual transistor dimensions remain tens of nm; quantum tunneling concerns are raised but not deeply resolved.
  • Several note SRAM and interconnect scaling are now much worse than logic scaling, limiting uniform density gains.
  • There’s a shared sense that Moore/Dennard‑style easy doubling is over; future gains will be smaller, more conditional, and more expensive.

3D and Alternative Approaches

  • Readers ask why not go “truly 3D” instead of ever‑smaller nodes. Responses emphasize heat removal, power delivery, and process difficulty; current realistic options are limited stacking of dies or transistor layers.
  • 3D NAND and stacked SRAM are cited as working examples, but general‑purpose logic stacking is seen as constrained.

Business, Strategy, and Governance

  • Long subthread on Intel’s EUV delay: some blame “MBA mentality” and finance‑driven leadership; others point out key missteps came from engineer‑CEOs and from over‑ambitious, risky 10nm plans.
  • Broader debate: can non‑technical MBAs successfully run engineering companies, and how much process failures were due to risk aversion vs overreach.
  • Some see AI demand (training and especially inference) creating huge new foundry opportunities; others warn AI could be a bubble and data‑center‑only demand may not sustain massive fab spending.

Marketing, Units, and Naming Frustrations

  • Many are irritated by nm and Å labels that don’t map to physical lengths; some suggest calling them “marketing nanometers” or just versioned names like “N3, N2”.
  • Mixed views on whether this really matters: designers look at detailed PPA data; end users mostly need to know “smaller number ≈ better generation.”