Barcelona Supercomputing Center presents Sargantana: new open-source RISC-V chip

Original Article ↗ Hacker News Discussion ↗

Barcelona Supercomputing Center has unveiled Sargantana, an open-source RISC‑V processor designed in Spain and fabricated on a 22nm FD‑SOI process, aimed at scientific, real‑time, and high‑performance computing rather than consumer devices. Commenters examine its technical trade-offs (in-order vs out-of-order features, vector extensions, modest benchmark scores), the choice of a mature process node, and the availability of its RTL on GitHub. The launch also prompts broader reflections on European chip sovereignty, the economics of building non‑cutting‑edge fabs, and the growing but still uneven maturity of the RISC‑V hardware ecosystem.

Background and BSC context

  • Commenters note BSC’s broader profile: hosts the MareNostrum supercomputers (one famously in a chapel), co‑hosted a RISC‑V summit, and runs open research projects (HPC workflows, climate work, language tech like Catalan NLP).
  • Some see Sargantana as part of Europe’s push for more open, locally designed compute and reduced dependence on large foreign vendors.

Architecture and technical details

  • Linked preprint: 22nm FD‑SOI, RV64G (some confusion in the thread about “GC”), with a subset of the pre‑1.0 RISC‑V vector extension (v0.7.1).
  • Nominal ~1.26 GHz clock; architecture described as a 7‑stage pipeline with some out‑of‑order features (register renaming, non‑blocking memory) on top of a previously in‑order design.
  • Fabrication likely at GlobalFoundries in Germany, based on the node.

Performance and design tradeoffs

  • Benchmarks: CoreMark/MHz ≈ 2.44; Dhrystone IPC ≈ 0.7. Several posters judge this as low for the complexity (OoO elements), suggesting a simpler core with more tuning might have been better.
  • Comparisons are made to existing open RISC‑V cores (e.g., Rocket, BOOM, PULP’s Spatz), with some wondering why not build on those instead of “not invented here.”
  • Others emphasize that 22nm is appropriate for many applications; expecting 4nm from such a project is seen as unrealistic.

Target applications and ecosystem

  • Paper and comments position Sargantana for industrial, scientific, real‑time, and HPC‑adjacent use, not consumer desktops or gaming.
  • Some hope it becomes a high‑end MCU‑style core; others think its performance is underwhelming for general‑purpose CPUs.
  • Broader RISC‑V ecosystem: discussion of various dev boards (VisionFive 2, Lichee Pi 4A, Milk‑V, Kendryte K230) and the need for real hardware vs emulation for benchmarking. Mixed views on current RISC‑V performance vs x86.

Open-source status

  • One commenter initially doubts the “open source” label but is pointed to the publicly available RTL on GitHub, confirming it is indeed open hardware.

European fabs and strategic autonomy

  • Long subthread on EU semiconductor capability:
    • Agreement that 20–40nm and 22/28nm nodes cover most non‑bleeding‑edge needs and are important for security and supply resilience.
    • Debate over how many sub‑28nm fabs exist in Europe, profitability of new older‑node fabs, and whether state subsidies and “strategic loss‑leaders” are justified.
    • Discussion of lifecycle economics: older fabs only make cheap chips profitably after years of high‑margin production; restarting or building such capacity from scratch is costly and fragile.
    • Some argue stockpiling legacy parts and using specialized vendors may be more realistic than full on‑shoring.

Naming, language, and cultural tangents

  • “Sargantana” is Catalan for a local lizard; part of a lizard‑themed chip family (“Lagarto”).
  • Extended side debate about “Spanish” vs “Castilian” terminology and non‑Castilian languages in Spain and Latin America.
  • Brief note that BSC and its chapel‑hosted supercomputer also feature in media and even ambient music recordings.