AMD Zen 5 CPUs Reportedly Made on TSMC's 3nm Process, Mass Production in Q3

Original Article ↗ Hacker News Discussion ↗

Reports that AMD’s upcoming Zen 5 CPUs will use TSMC’s 3nm process prompt scrutiny of the actual roadmap, with some sources indicating mainstream Zen 5 will remain on 4nm while only dense Zen 5C variants move to 3nm. Commenters weigh whether to delay new PC builds for Zen 5/X3D and improved AM5 motherboards, while also debating how much process node, memory bandwidth, and on‑package RAM versus ISA (x86 vs ARM) really explain the efficiency gap between Apple’s M‑series chips and current AMD/Intel offerings. Overall, many argue that design goals, ecosystem, and power targets now matter more than instruction set in determining real-world performance and perf‑per‑watt.

Process node claims & article reliability

  • TSMC has two 3nm lines; one is Apple-only, the other reportedly booked by AMD and possibly Nvidia.
  • The headline is viewed as clickbait: the body of the (blogspam) article says Zen 5 desktop uses 4nm, while Zen 5C uses 3nm, and may mix up core variants.
  • Node shrink expectations discussed: ~20% speed/power-per-area and ~20% density, but SRAM scaling is weaker.

PC build timing & AM5 platform

  • Many commenters wrestle with “buy now vs wait”: 7800X3D vs a future 8800X3D/9800X3D.
  • Arguments for buying now: hardware is already excellent; next-gen is always “around the corner”; AM5 allows later CPU drops.
  • Arguments for waiting: X3D models typically lag ~6 months; next-gen boards may add USB4, better I/O, new power connectors, and more mature firmware.
  • RAM prices are expected by some to rise sharply, so buying memory early is suggested.

Motherboards, RAM, and platform quirks

  • Mixed experiences with AM5: some report very stable systems; others report terrible BIOS quality, long boot times, EXPO/XMP instability, suspend issues.
  • Vendor reputation varies by commenter; one notes past overvolting incidents killing CPUs.
  • Running 4 DIMMs at high speed on AM5 is problematic; advice leans toward 2×32 GB high-quality DDR5 kits.

Zen 5 expectations

  • Speculation that extra density may allow 512‑bit FPUs and larger core structures.
  • Rumored Cinebench leaks suggest ~15% multicore uplift and much higher AVX-heavy single-core gains, but numbers are treated cautiously.

Apple M‑series vs AMD/Intel

  • Some want Zen 5 benchmarks to test the claim that Apple’s lead is mostly process-node driven.
  • Others note that AMD is already close to M‑series efficiency under load, but worse at idle.
  • Debate over performance:
    • Some say modern AMD is already faster overall and Apple mainly wins on perf/watt.
    • Others cite benchmarks where Apple leads in single-core but trails in multi-core, with price hard to compare since Apple CPUs aren’t sold standalone.
  • Apple’s advantage is also tied to high memory bandwidth from on-package unified memory, not just node.

x86 vs ARM efficiency and ISA debate

  • Several argue ISA (x86 vs ARM) matters little today compared to node, design goals, and bandwidth; both are effectively “CISC” in practice with micro-op translation.
  • Others discuss x86 decode complexity vs fixed-width ARM, but note predictors and compilers mitigate this.
  • One oversimplified view (ARM great at light tasks, collapses under heavy multitasking) is challenged as inaccurate and unsupported.

Mobile CPUs & battery life

  • Desire for x86 laptops with MacBook‑like battery life and no throttling.
  • Reports that AMD mobile can idle at ~6–8 W whole-system; Intel older 14 nm laptops can idle under 5 W.
  • Some see AMD generally more efficient than Intel under load, but not at idle; individual experiences vary widely by model, OS, and tuning.

Memory bandwidth & on‑package RAM future

  • Apple’s bandwidth lead attributed to many memory channels via on‑package RAM.
  • Discussion that AMD/Intel may eventually adopt on‑package RAM more broadly (already used in HBM server parts), but it would affect socket compatibility and segmentation.
  • Upcoming AMD designs (e.g., Strix Halo) may rely more on large caches plus fewer channels, trading raw bandwidth for efficiency and capacity options.

Datacenter implications

  • One comment wonders when compute density will exceed needs, noting that replacing 5–7‑year‑old servers with Zen 5c EPYC could theoretically cut server count by ~70% or more.