Intel, Samsung, and TSMC Demo 3D-Stacked Transistors

Original Article ↗ Hacker News Discussion ↗

Chipmakers Intel, Samsung and TSMC are prototyping 3D‑stacked “complementary FETs” (CFETs), which place n‑ and p‑type transistors vertically to squeeze more logic into the same footprint and improve power efficiency. Commenters note that while this won’t enable magical “3 nm apart” layouts, it could yield perhaps 30–40% density gains, better performance per watt, and new options for integrating memory and cache, all without fundamentally changing how chips are programmed. Much of the debate centers on practical limits: heat density and cooling, SRAM and cache scaling, defect-driven costs on larger dies, and whether economic rather than physical constraints will ultimately slow Moore’s law.

Scope of the 3D-Stacked Transistor / CFET Advance

  • “3 nm / 5 nm” marketing names hide that actual device pitches here are ~45–60 nm; you can’t place transistors 3–5 nm apart.
  • Expected density gain is roughly 30–40% more transistors in the same area.
  • CFETs are seen as an evolutionary step: similar logic as FinFET/GAAFET, but better power/performance, not a new computing paradigm.
  • Some speculate about tighter DRAM integration or chiplets with large on-package RAM, but this is not demonstrated in the article.

Heat, Power, and Cooling

  • Several commenters worry 3D-stacking will worsen heat removal and cap clock speeds.
  • Counterpoint: CFETs stack devices vertically within the same “layer,” not like stacking whole dies; heat density remains the key issue, not “buried” hot chips.
  • Backside power delivery is highlighted as important for both power efficiency and cooling.
  • Proposed future cooling ideas include: dual-sided cooling, built-in fins on the motherboard, or even on-chip liquid cooling channels; others doubt radical socket/board changes will be practical.
  • A simple conduction argument claims a few extra tens of nanometers of silicon won’t create major temperature gradients between stacked devices.

Clock Speed vs. Cores / IPC

  • Frequency is seen as fundamentally tied to heat; 3D stacking is unlikely to increase GHz.
  • Better performance is expected mainly from higher density, more cores, and possibly higher IPC, not big clock jumps.

Density, Cost, and Chip Size

  • Question: why not just use bigger chips instead of ever-denser transistors?
  • Responses:
    • Larger dies suffer much worse yield due to defects; cost scales strongly with area.
    • Long-distance signaling needs more power and can limit frequency.
    • Lithography fields (~25×35 mm) constrain practical “spreading out.”
    • Chiplets are one way to get large logical chips from smaller physical dies.

Moore’s Law, Limits, and Economics

  • Some emphasize real physical and architectural limits: Dennard scaling is dead, heat and SRAM scaling are major constraints, dark silicon is increasing.
  • Others argue the main bottleneck has long been economics and market size; smartphone and AI demand have pushed nodes far beyond older projections.
  • There is debate over how much headroom remains (from “nowhere near the limit” to “maybe <100× left by 2030”), but consensus that further progress is harder and costlier.

3D NAND vs. Logic Reliability

  • One subthread warns about 3D NAND issues (read disturb, retention, layer variation) and suggests stacked logic might bring similar reliability or even security surprises.
  • Replies argue dense volatile logic is a different regime: it need not retain state, and process kinks are typically engineered around by specialized memory vendors.
  • There is debate over whether 3D NAND endurance specs adequately capture read-induced wear; some see it as acceptable trade-off, others as planned obsolescence.